1. Field of Invention
The present invention relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method of forming a self-aligned dynamic random access memory (DRAM) cell.
2. Description of Related Art
FIGS. 1A through 1E are schematic cross-sectional views showing the progression of steps for forming a conventional DRAM cell. First, as shown in FIG. 1A, shallow trench isolation (STI) structures 102 are formed in a silicon substrate 100. The STI structures dissect the substrate into separate cell regions. Transistors 104 and 106 are formed above the substrate 100. Since conventional methods are used to form the transistors 104 and 106, detailed descriptions are omitted here. The transistors 104 and 106 consist of a gate conductive layer 108, a gate oxide layer 110, source/drain regions 112, a cap layer 114 and silicon nitride spacers 116.
As shown in FIG. 1B, a dielectric layer 118 is formed over the substrate 100 covering the transistors 104, 106 (FIG. 1) and the isolating structures 102. Photolithographic and etching techniques are used to pattern the dielectric layer 118 to form a bit line contact opening 120 that exposes the source/drain region 112. Polysilicon is then deposited into the opening 120 and over the dielectric layer 118 to form a polysilicon layer 122.
As shown in FIG. 1C, photolithographic and etching techniques are again used to pattern the polysilicon layer 122 to form a bit line 124 in the contact opening 120. Another dielectric layer 126 is formed over the dielectric layer 118. Using photolithographic and etching techniques, the dielectric layers 126 and 120 are patterned to form a node contact opening 128, as shown in FIG. 1D.
As shown in FIG. 1E, a contact plug 130 is formed inside the node contact opening 128. A bottom electrode 134 is next formed over the contact plug 130.
As the level of integration of devices on a chip continues to increase, the contact opening 120 in the first layer and the node contact opening 128 are formed increasingly closer to each other. In addition, the aspect ratio of the node contact opening 128 is relatively large. Consequently, particles produced during an etching operation may accumulate near the bottom of the opening. Since these particles are difficult to remove by ordinary cleaning processes, they will likely remain and lead to an increase in junction resistance with a subsequently formed conductive layer.
Furthermore, if the contact opening 128 is slightly misaligned, a portion of the isolating structure 102 may be etched leading to a leakage current. Moreover, silicon nitride spacers 116 often produce internal stresses. Thus, refreshing operations need to be carried out more often.